From 9a6bfb8f8aab0e4811c7171475f2b763048df431 Mon Sep 17 00:00:00 2001 From: Ian C Date: Sat, 26 Aug 2006 23:09:04 +0000 Subject: Checkin prior to replacing some of the opcode routines. --- z80_decode.c | 89 ++++++++++++++++++++++++++++++------------------------------ 1 file changed, 45 insertions(+), 44 deletions(-) (limited to 'z80_decode.c') diff --git a/z80_decode.c b/z80_decode.c index 52a0423..b692615 100644 --- a/z80_decode.c +++ b/z80_decode.c @@ -217,12 +217,12 @@ do { \ do { \ Z80Word VAL=ONCE; \ Z80Val w; \ - w=REG+(Z80Val)VAL; \ + w=(REG)+(Z80Val)VAL; \ cpu->AF.b[LO]&=(S_Z80|Z_Z80|V_Z80); \ if (w>0xffff) cpu->AF.b[LO]|=C_Z80; \ - if ((REG^w^VAL)&0x1000) cpu->AF.b[LO]|=H_Z80; \ + if (((REG)^w^VAL)&0x1000) cpu->AF.b[LO]|=H_Z80; \ SETHIDDEN(w>>8); \ - REG=w; \ + (REG)=w; \ } while(0) @@ -230,14 +230,14 @@ do { \ do { \ Z80Word VAL=ONCE; \ Z80Val w; \ - w=REG+(Z80Val)VAL+CARRY; \ + w=(REG)+(Z80Val)VAL+CARRY; \ cpu->AF.b[LO]=0; \ if ((w&0xffff)==0) cpu->AF.b[LO]=Z_Z80; \ if (w>0xffff) cpu->AF.b[LO]|=C_Z80; \ - if ((VAL^REG^0x8000)&(REG^w)&0x8000) cpu->AF.b[LO]|=P_Z80; \ - if ((REG^w^VAL)&0x1000) cpu->AF.b[LO]|=H_Z80; \ + if ((VAL^(REG)^0x8000)&((REG)^w)&0x8000) cpu->AF.b[LO]|=P_Z80; \ + if (((REG)^w^VAL)&0x1000) cpu->AF.b[LO]|=H_Z80; \ SETHIDDEN(w>>8); \ - REG=w; \ + (REG)=w; \ } while(0) @@ -245,35 +245,35 @@ do { \ do { \ Z80Word VAL=ONCE; \ Z80Val w; \ - w=REG-(Z80Val)VAL-CARRY; \ + w=(REG)-(Z80Val)VAL-CARRY; \ cpu->AF.b[LO]=N_Z80; \ if ((w&0xffff)==0) cpu->AF.b[LO]=Z_Z80; \ if (w&0x8000) cpu->AF.b[LO]|=S_Z80; \ if ((w&0xffff)==0) cpu->AF.b[LO]|=Z_Z80; \ if (w>0xffff) cpu->AF.b[LO]|=C_Z80; \ - if ((VAL^REG)&(VAL^w)&0x8000) cpu->AF.b[LO]|=P_Z80; \ - if ((REG^w^VAL)&0x1000) cpu->AF.b[LO]|=H_Z80; \ + if ((VAL^(REG))&(VAL^w)&0x8000) cpu->AF.b[LO]|=P_Z80; \ + if (((REG)^w^VAL)&0x1000) cpu->AF.b[LO]|=H_Z80; \ SETHIDDEN(w>>8); \ - REG=w; \ + (REG)=w; \ } while(0) #define INC8(REG) \ do { \ - REG++; \ - cpu->AF.b[LO]=CARRY|SZtable[REG]; \ - if (REG==0x80) cpu->AF.b[LO]|=P_Z80; \ - if ((REG&0x0f)==0) cpu->AF.b[LO]|=H_Z80; \ + (REG)++; \ + cpu->AF.b[LO]=CARRY|SZtable[(REG)]; \ + if ((REG)==0x80) cpu->AF.b[LO]|=P_Z80; \ + if (((REG)&0x0f)==0) cpu->AF.b[LO]|=H_Z80; \ } while(0) #define DEC8(REG) \ do { \ - REG--; \ + (REG)--; \ cpu->AF.b[LO]=N_Z80|CARRY; \ - if (REG==0x7f) cpu->AF.b[LO]|=P_Z80; \ - if ((REG&0x0f)==0x0f) cpu->AF.b[LO]|=H_Z80; \ - cpu->AF.b[LO]|=SZtable[REG]; \ + if ((REG)==0x7f) cpu->AF.b[LO]|=P_Z80; \ + if (((REG)&0x0f)==0x0f) cpu->AF.b[LO]|=H_Z80; \ + cpu->AF.b[LO]|=SZtable[(REG)]; \ } while(0) @@ -300,9 +300,9 @@ do { \ #define RRC(REG) \ do { \ Z80Byte c; \ - c=REG&C_Z80; \ - REG=(REG>>1)|(REG<<7); \ - cpu->AF.b[LO]=PSZtable[REG]|c; \ + c=(REG)&C_Z80; \ + (REG)=((REG)>>1)|((REG)<<7); \ + cpu->AF.b[LO]=PSZtable[(REG)]|c; \ SETHIDDEN(REG); \ } while(0) @@ -310,9 +310,9 @@ do { \ #define RR(REG) \ do { \ Z80Byte c; \ - c=REG&C_Z80; \ - REG=(REG>>1)|(CARRY<<7); \ - cpu->AF.b[LO]=PSZtable[REG]|c; \ + c=(REG)&C_Z80; \ + (REG)=((REG)>>1)|(CARRY<<7); \ + cpu->AF.b[LO]=PSZtable[(REG)]|c; \ SETHIDDEN(REG); \ } while(0) @@ -338,9 +338,9 @@ do { \ #define RLC(REG) \ do { \ Z80Byte c; \ - c=REG>>7; \ - REG=(REG<<1)|c; \ - cpu->AF.b[LO]=PSZtable[REG]|c; \ + c=(REG)>>7; \ + (REG)=((REG)<<1)|c; \ + cpu->AF.b[LO]=PSZtable[(REG)]|c; \ SETHIDDEN(REG); \ } while(0) @@ -348,9 +348,9 @@ do { \ #define RL(REG) \ do { \ Z80Byte c; \ - c=REG>>7; \ - REG=(REG<<1)|CARRY; \ - cpu->AF.b[LO]=PSZtable[REG]|c; \ + c=(REG)>>7; \ + (REG)=((REG)<<1)|CARRY; \ + cpu->AF.b[LO]=PSZtable[(REG)]|c; \ SETHIDDEN(REG); \ } while(0) @@ -358,9 +358,9 @@ do { \ #define SRL(REG) \ do { \ Z80Byte c; \ - c=REG&C_Z80; \ - REG>>=1; \ - cpu->AF.b[LO]=PSZtable[REG]|c; \ + c=(REG)&C_Z80; \ + (REG)>>=1; \ + cpu->AF.b[LO]=PSZtable[(REG)]|c; \ SETHIDDEN(REG); \ } while(0) @@ -368,9 +368,9 @@ do { \ #define SRA(REG) \ do { \ Z80Byte c; \ - c=REG&C_Z80; \ - REG=(REG>>1)|(REG&0x80); \ - cpu->AF.b[LO]=PSZtable[REG]|c; \ + c=(REG)&C_Z80; \ + (REG)=((REG)>>1)|((REG)&0x80); \ + cpu->AF.b[LO]=PSZtable[(REG)]|c; \ SETHIDDEN(REG); \ } while(0) @@ -378,9 +378,9 @@ do { \ #define SLL(REG) \ do { \ Z80Byte c; \ - c=REG>>7; \ - REG=(REG<<1)|1; \ - cpu->AF.b[LO]=PSZtable[REG]|c; \ + c=(REG)>>7; \ + (REG)=((REG)<<1)|1; \ + cpu->AF.b[LO]=PSZtable[(REG)]|c; \ SETHIDDEN(REG); \ } while(0) @@ -388,9 +388,9 @@ do { \ #define SLA(REG) \ do { \ Z80Byte c; \ - c=REG>>7; \ - REG=REG<<1; \ - cpu->AF.b[LO]=PSZtable[REG]|c; \ + c=(REG)>>7; \ + (REG)=(REG)<<1; \ + cpu->AF.b[LO]=PSZtable[(REG)]|c; \ SETHIDDEN(REG); \ } while(0) @@ -424,7 +424,7 @@ do { \ #define BIT(REG,B) \ do { \ cpu->AF.b[LO]=CARRY|H_Z80; \ - if (REG&&(1<AF.b[LO]|=S_Z80; \ if (B==5) cpu->AF.b[LO]|=B5_Z80; \ @@ -433,6 +433,7 @@ do { \ else \ { \ cpu->AF.b[LO]|=Z_Z80; \ + cpu->AF.b[LO]|=P_Z80; \ } \ } while(0) -- cgit v1.2.3