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1 files changed, 1576 insertions, 0 deletions

diff --git a/z80_decode.c b/z80_decode.c
new file mode 100644
index 0000000..c323d1f
--- /dev/null
+++ b/z80_decode.c
@@ -0,0 +1,1576 @@
+/*
+
+    z80 - Z80 Emulator
+
+    Copyright (C) 2006  Ian Cowburn <ianc@noddybox.co.uk>
+
+    Some of the opcode routines are based on the Z80 emulation from YAZE,
+    Copyright (c) 1995 Frank D. Cringle.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+    -------------------------------------------------------------------------
+
+    $Id$
+
+    Z80
+
+*/
+#include "z80_private.h"
+
+/* ---------------------------------------- ARITHMETIC OPS
+*/
+#define ADD_8_BIT(REG,VAL)					\
+do								\
+{								\
+    Z80Word w;							\
+    w=REG+(Z80Word)VAL;						\
+    cpu->F=SZtable[w];						\
+    if ((REG^w^VAL)&H_Z80) cpu->F|=H_Z80;			\
+    if ((VAL^REG^0x80)&(REG^w)&0x80) cpu->F|=P_Z80;		\
+    SETHIDDEN(w);						\
+    REG=w;							\
+} while(0)
+
+
+#define ADC_8_BIT(REG,VAL)					\
+do								\
+{								\
+    Z80Word w;							\
+    w=(REG+(Z80Word)VAL+CARRY)&0x1ff;				\
+    cpu->F=SZtable[w];						\
+    if ((REG^w^VAL)&H_Z80) cpu->F|=H_Z80;			\
+    if ((VAL^REG^0x80)&(REG^w)&0x80) cpu->F|=P_Z80;		\
+    SETHIDDEN(w);						\
+    REG=w;							\
+} while(0)
+
+
+#define SUB_8_BIT(REG,VAL)					\
+do								\
+{								\
+    Z80Word w;							\
+    w=(REG-(Z80Word)VAL)&0x1ff;					\
+    cpu->F=SZtable[w]|N_Z80;					\
+    if ((REG^w^VAL)&H_Z80) cpu->F|=H_Z80;			\
+    if ((VAL^REG^0x80)&(REG^w)&0x80) cpu->F|=P_Z80;		\
+    SETHIDDEN(w);						\
+    REG=w;							\
+} while(0)
+
+
+#define CMP_8_BIT(REG,VAL)					\
+do								\
+{								\
+    Z80Word w;							\
+    w=(REG-(Z80Word)VAL)&0x1ff;					\
+    cpu->F=SZtable[w]|N_Z80;					\
+    if ((REG^w^VAL)&H_Z80) cpu->F|=H_Z80;			\
+    if ((VAL^REG^0x80)&(REG^w)&0x80) cpu->F|=P_Z80;		\
+    SETHIDDEN(VAL);						\
+} while(0)
+
+
+#define SBC_8_BIT(REG,VAL)					\
+do								\
+{								\
+    Z80Word w;							\
+    w=(REG-(Z80Word)VAL-CARRY)&0x1ff;				\
+    cpu->F=SZtable[w]|N_Z80;					\
+    if ((REG^w^VAL)&H_Z80) cpu->F|=H_Z80;			\
+    if ((VAL^REG^0x80)&(REG^w)&0x80) cpu->F|=P_Z80;		\
+    SETHIDDEN(w);						\
+    REG=w;							\
+} while(0)
+
+
+#define ADD_16_BIT(REG,VAL)					\
+do								\
+{								\
+    Z80Val w;							\
+    w=REG+(Z80Val)VAL;						\
+    cpu->F&=(S_Z80|Z_Z80|V_Z80);				\
+    if (w>0xffff) cpu->F|=C_Z80;				\
+    if ((REG^w^VAL)&0x1000) cpu->F|=H_Z80;			\
+    SETHIDDEN(w>>8);						\
+    REG=w;							\
+} while(0)
+
+
+#define ADC_16_BIT(REG,VAL)					\
+do								\
+{								\
+    Z80Val w;							\
+    w=REG+(Z80Val)VAL+CARRY;					\
+    cpu->F&=(S_Z80|Z_Z80|V_Z80);				\
+    if (w>0xffff) cpu->F|=C_Z80;				\
+    if ((REG^w^VAL)&0x1000) cpu->F|=H_Z80;			\
+    SETHIDDEN(w>>8);						\
+    REG=w;							\
+} while(0)
+
+
+#define SBC_16_BIT(REG,VAL)					\
+do								\
+{								\
+    Z80Val w;							\
+    w=REG-(Z80Val)VAL-CARRY;					\
+    cpu->F=N_Z80;						\
+    if (w&0x8000) cpu->F|=S_Z80;				\
+    if ((w&0xffff)==0) cpu->F|=Z_Z80;				\
+    if (w>0xffff) cpu->F|=C_Z80;				\
+    if ((REG^w^VAL)&0x1000) cpu->F|=H_Z80;			\
+    if ((VAL^REG)&(VAL^w)&0x8000) cpu->F|=P_Z80;		\
+    SETHIDDEN(w>>8);						\
+    REG=w;							\
+} while(0)
+
+
+#define INC8(REG)						\
+do								\
+{								\
+    REG++;							\
+    cpu->F=CARRY|SZtable[REG];					\
+    if (w&0x80) cpu->F|=P_Z80;					\
+    if (w&0x0f) cpu->F|=H_Z80;					\
+} while(0)
+
+
+#define DEC8(REG)						\
+do								\
+{								\
+    cpu->F=N_Z80|CARRY;						\
+    if (w&0x80) cpu->F|=P_Z80;					\
+    if (w&0x0f) cpu->F|=H_Z80;					\
+    REG--;							\
+    cpu->F|=SZtable[REG];					\
+} while(0)
+
+
+/* ---------------------------------------- ROTATE AND SHIFT OPS
+*/
+#define RRCA							\
+do								\
+{								\
+    cpu->F=(cpu->F&0xec)|cpu->A&C_Z80;				\
+    cpu->A=(cpu->A>>1)|(cpu->A<<7);				\
+    SETHIDDEN(cpu->A);						\
+} while(0)
+
+
+#define RRA							\
+do								\
+{								\
+    Z80Byte c;							\
+    c=CARRY;							\
+    cpu->F=(cpu->F&0xec)|cpu->A&C_Z80;				\
+    cpu->A=(cpu->A>>1)|(c<<7);					\
+    SETHIDDEN(cpu->A);						\
+} while(0)
+
+
+#define RRC(REG)						\
+do								\
+{								\
+    Z80Byte c;							\
+    c=REG&C_Z80;						\
+    REG=(REG>>1)|(REG<<7);					\
+    cpu->F=PSZtable[REG]|c;					\
+    SETHIDDEN(REG);						\
+} while(0)
+
+
+#define RR(REG)							\
+do								\
+{								\
+    Z80Byte c;							\
+    c=REG&C_Z80;						\
+    REG=(REG>>1)|(CARRY<<7);					\
+    cpu->F=PSZtable[REG]|c;					\
+    SETHIDDEN(REG);						\
+} while(0)
+
+
+#define RLCA							\
+do								\
+{								\
+    cpu->F=(cpu->F&0xec)|(cpu->A>>7);				\
+    cpu->A=(cpu->A<<1)|(cpu->A>>7);				\
+    SETHIDDEN(cpu->A);						\
+} while(0)
+
+
+#define RLA							\
+do								\
+{								\
+    Z80Byte c;							\
+    c=CARRY;							\
+    cpu->F=(cpu->F&0xec)|(cpu->A>>7);				\
+    cpu->A=(cpu->A<<1)|c;					\
+    SETHIDDEN(cpu->A);						\
+} while(0)
+
+
+#define RLC(REG)						\
+do								\
+{								\
+    Z80Byte c;							\
+    c=REG>>7;							\
+    REG=(REG<<1)|c;						\
+    cpu->F=PSZtable[REG]|c;					\
+    SETHIDDEN(REG);						\
+} while(0)
+
+
+#define RL(REG)							\
+do								\
+{								\
+    Z80Byte c;							\
+    c=REG>>7;							\
+    REG=(REG<<1)|CARRY;						\
+    cpu->F=PSZtable[REG]|c;					\
+    SETHIDDEN(REG);						\
+} while(0)
+
+
+#define SRL(REG)						\
+do								\
+{								\
+    Z80Byte c;							\
+    c=REG&Z80_C;						\
+    REG>>=1;							\
+    cpu->F=PSZtable[REG]|c;					\
+    SETHIDDEN(REG);						\
+} while(0)
+
+
+#define SRA(REG)						\
+do								\
+{								\
+    Z80Byte c;							\
+    c=REG&Z80_C;						\
+    REG=(REG>>1)|(REG&0x80);					\
+    cpu->F=PSZtable[REG]|c;					\
+    SETHIDDEN(REG);						\
+} while(0)
+
+
+#define SLL(REG)						\
+do								\
+{								\
+    Z80Byte c;							\
+    c=REG>>7;							\
+    REG=(REG<<1)|1;						\
+    cpu->F=PSZtable[REG]|c;					\
+    SETHIDDEN(REG);						\
+} while(0)
+
+
+#define SLA(REG)						\
+do								\
+{								\
+    Z80Byte c;							\
+    c=REG>>7;							\
+    REG=REG<<1;							\
+    cpu->F=PSZtable[REG]|c;					\
+    SETHIDDEN(REG);						\
+} while(0)
+
+
+/* ---------------------------------------- FLOW OPS
+*/
+#define CALL(COND)						\
+do								\
+{								\
+    if (COND)							\
+    {								\
+	PUSH(cpu->PC+2);					\
+	cpu->PC=PEEKW(cpu->PC);					\
+    }								\
+    else							\
+    {								\
+    	cpu->PC+=2;						\
+    }								\
+}								\
+while(0)
+
+
+#define JP(COND)						\
+do								\
+{								\
+    if (COND)							\
+    {								\
+	cpu->PC=PEEKW(cpu->PC);					\
+    }								\
+    else							\
+    {								\
+    	cpu->PC+=2;						\
+    }								\
+}								\
+while(0)
+
+
+#define JR(COND)						\
+do								\
+{								\
+    if (COND)							\
+    {								\
+	cpu->PC+=(Z80Relative)PEEK(cpu->PC)+1;			\
+    }								\
+    else							\
+    {								\
+    	cpu->PC++;						\
+    }								\
+}								\
+while(0)
+
+
+/* ---------------------------------------- BOOLEAN OPS
+*/
+#define AND(REG,VAL)						\
+do								\
+{								\
+    REG&=VAL;							\
+    cpu->F=PSZtable[REG]|H_Z80;					\
+    SETHIDDEN(REG);						\
+} while(0)
+
+
+#define OR(REG,VAL)						\
+do								\
+{								\
+    REG|=VAL;							\
+    cpu->F=PSZtable[REG];					\
+    SETHIDDEN(REG);						\
+} while(0)
+
+
+#define XOR(REG,VAL)						\
+do								\
+{								\
+    REG^=VAL;							\
+    cpu->F=PSZtable[REG];					\
+    SETHIDDEN(REG);						\
+} while(0)
+
+
+#define BIT(REG,B)						\
+do								\
+{								\
+    cpu->F=CARRY|H_Z80;						\
+    if (REG&&(1<<B))						\
+    {								\
+    	if (B==7) cpu->F|=S_Z80;				\
+	if (B==5) cpu->F|=B5_Z80;				\
+	if (B==3) cpu->F|=B3_Z80;				\
+    }								\
+    else							\
+    {								\
+    	cpu->F|=Z_Z80;						\
+    }								\
+} while(0)
+
+
+/* ---------------------------------------- GENERAL MACROS
+*/
+
+/* Decides whether the offset for IX/IY should be fetched, or used
+   from the store for a CB instruction
+*/
+#define GETREL	(cpu->use_cb_off ? cpu->cb_off : (Z80Relative)FETCH_BYTE)
+
+
+/* ---------------------------------------- GENERAL UTILS
+*/
+
+/* This code based on the DAA opcode from YAZE, (c) Frank D. Cringle
+*/
+static void DAA (Z80 *cpu)
+{
+    Z80Word AF;
+    Z80Word acu,temp,cbits;
+
+    AF=(Z80Word)cpu->A<<8|cpu->F;
+    acu=cpu->A;
+    temp=acu&0xf;
+    cbits=CARRY;
+
+    if (IS_N)       /* last operation was a subtract */
+    {
+	int hd = cbits || acu > 0x99;
+	if (IS_H || (temp > 9)) /* adjust low digit */
+	{
+	    if (temp > 5)
+	    {
+		CLR(AF,H_Z80);
+	    }
+
+	    acu -= 6;
+	    acu &= 0xff;
+	}
+	if (hd)         /* adjust high digit */
+	    acu -= 0x160;
+    }
+    else                  /* last operation was an add */
+    {
+	if (IS_H || (temp > 9)) /* adjust low digit */
+	{
+	    if (temp>9)
+	    {
+	    	SET(AF,H_Z80);
+	    }
+	    else
+	    {
+	    	CLR(AF,H_Z80);
+	    }
+	    acu += 6;
+	}
+	if (cbits || ((acu & 0x1f0) > 0x90)) /* adjust high digit */
+	    acu += 0x60;
+    }
+
+    cbits |= (acu >> 8) & 1;
+    acu &= 0xff;
+    AF = (acu << 8) | (acu & 0xa8) | ((acu == 0) << 6) |
+	    (AF & 0x12) | partab[acu] | cbits;
+
+    cpu->A=(AF>>8);
+    cpu->F=(AF&0xff);
+    SETHIDDEN(cpu->A);
+}
+
+
+
+/* ---------------------------------------- HANDLERS FOR CB OPCODES
+*/
+static void DecodeCB(Z80 *cpu, Z80Byte opcode)
+{
+    switch(opcode)
+    {
+    }
+
+    Z80Byte bmh,bmm,bml;
+
+    /* Split up the opcode into it's bitmasks
+    */
+    bmh=(opcode>>6)&3;
+    bmm=(opcode>>3)&7;
+    bml=opcode&7;
+
+    /* Instruction set 00
+    */
+    if (bmh==0x00)
+    {
+    	CBOp_00(cpu,opcode,bmh,bmm,bml);
+	return;
+    }
+
+    /* Instruction set 01 (BIT)
+    */
+    if (bmh==0x01)
+    {
+    	CBOp_01(cpu,opcode,bmh,bmm,bml);
+	return;
+    }
+
+    /* Instruction set 10 (RES) and 11 (SET)
+    */
+    CBOp_ResSet(cpu,opcode,bmh,bmm,bml);
+}
+
+
+
+
+/* ---------------------------------------- OPCODE DECODER
+*/
+void Z80_Decode(Z80 *cpu, Z80Byte opcode)
+{
+    Z80Byte bmh,bmm,bml;
+
+    /* IX/IY shifts
+    */
+    if (opcode==0xdd || opcode==0xfd)
+    {
+	TSTATE(4);
+	INC_R;
+
+    	cpu->shift=opcode;
+	Z80_Decode(cpu,FETCH_BYTE);
+	return;
+    }
+
+    /* CB shifts
+    */
+    if (opcode==0xcb)
+    {
+	INC_R;
+
+	/* Check for previous IX/IY shift.
+	*/
+	if (cpu->shift!=0)
+	{
+	    cpu->use_cb_off=TRUE;
+	    cpu->cb_off=(Z80Relative)FETCH_BYTE;
+	}
+
+	DecodeCB(cpu,FETCH_BYTE);
+	return;
+    }
+
+    /* DE shifts
+    */
+    if (opcode==0xed)
+    {
+	INC_R;
+	DecodeED(cpu,FETCH_BYTE);
+	return;
+    }
+
+    *** NEW ***
+
+    INC_R;
+
+    switch(opcode)
+    {
+	case 0x00:	/* NOP */
+	    TSTATE(4);
+	    break;
+
+	case 0x01:	/* LD BC, nnnn */
+	    TSTATE(10);
+	    cpu->BC=FETCH_WORD;
+	    break;
+
+	case 0x02:
+	    TSTATE(7);
+	    break;
+
+	case 0x03:
+	    TSTATE(4);
+	    break;
+
+	case 0x04:
+	    TSTATE(4);
+	    break;
+
+	case 0x05:
+	    TSTATE(4);
+	    break;
+
+	case 0x06:
+	    TSTATE(4);
+	    break;
+
+	case 0x07:
+	    TSTATE(4);
+	    break;
+
+	case 0x08:
+	    TSTATE(4);
+	    break;
+
+	case 0x09:
+	    TSTATE(4);
+	    break;
+
+	case 0x0a:
+	    TSTATE(4);
+	    break;
+
+	case 0x0b:
+	    TSTATE(4);
+	    break;
+
+	case 0x0c:
+	    TSTATE(4);
+	    break;
+
+	case 0x0d:
+	    TSTATE(4);
+	    break;
+
+	case 0x0e:
+	    TSTATE(4);
+	    break;
+
+	case 0x0f:
+	    TSTATE(4);
+	    break;
+
+	case 0x10:
+	    TSTATE(4);
+	    break;
+
+	case 0x11:
+	    TSTATE(4);
+	    break;
+
+	case 0x12:
+	    TSTATE(4);
+	    break;
+
+	case 0x13:
+	    TSTATE(4);
+	    break;
+
+	case 0x14:
+	    TSTATE(4);
+	    break;
+
+	case 0x15:
+	    TSTATE(4);
+	    break;
+
+	case 0x16:
+	    TSTATE(4);
+	    break;
+
+	case 0x17:
+	    TSTATE(4);
+	    break;
+
+	case 0x18:
+	    TSTATE(4);
+	    break;
+
+	case 0x19:
+	    TSTATE(4);
+	    break;
+
+	case 0x1a:
+	    TSTATE(4);
+	    break;
+
+	case 0x1b:
+	    TSTATE(4);
+	    break;
+
+	case 0x1c:
+	    TSTATE(4);
+	    break;
+
+	case 0x1d:
+	    TSTATE(4);
+	    break;
+
+	case 0x1e:
+	    TSTATE(4);
+	    break;
+
+	case 0x1f:
+	    TSTATE(4);
+	    break;
+
+	case 0x20:
+	    TSTATE(4);
+	    break;
+
+	case 0x21:
+	    TSTATE(4);
+	    break;
+
+	case 0x22:
+	    TSTATE(4);
+	    break;
+
+	case 0x23:
+	    TSTATE(4);
+	    break;
+
+	case 0x24:
+	    TSTATE(4);
+	    break;
+
+	case 0x25:
+	    TSTATE(4);
+	    break;
+
+	case 0x26:
+	    TSTATE(4);
+	    break;
+
+	case 0x27:
+	    TSTATE(4);
+	    break;
+
+	case 0x28:
+	    TSTATE(4);
+	    break;
+
+	case 0x29:
+	    TSTATE(4);
+	    break;
+
+	case 0x2a:
+	    TSTATE(4);
+	    break;
+
+	case 0x2b:
+	    TSTATE(4);
+	    break;
+
+	case 0x2c:
+	    TSTATE(4);
+	    break;
+
+	case 0x2d:
+	    TSTATE(4);
+	    break;
+
+	case 0x2e:
+	    TSTATE(4);
+	    break;
+
+	case 0x2f:
+	    TSTATE(4);
+	    break;
+
+	case 0x30:
+	    TSTATE(4);
+	    break;
+
+	case 0x31:
+	    TSTATE(4);
+	    break;
+
+	case 0x32:
+	    TSTATE(4);
+	    break;
+
+	case 0x33:
+	    TSTATE(4);
+	    break;
+
+	case 0x34:
+	    TSTATE(4);
+	    break;
+
+	case 0x35:
+	    TSTATE(4);
+	    break;
+
+	case 0x36:
+	    TSTATE(4);
+	    break;
+
+	case 0x37:
+	    TSTATE(4);
+	    break;
+
+	case 0x38:
+	    TSTATE(4);
+	    break;
+
+	case 0x39:
+	    TSTATE(4);
+	    break;
+
+	case 0x3a:
+	    TSTATE(4);
+	    break;
+
+	case 0x3b:
+	    TSTATE(4);
+	    break;
+
+	case 0x3c:
+	    TSTATE(4);
+	    break;
+
+	case 0x3d:
+	    TSTATE(4);
+	    break;
+
+	case 0x3e:
+	    TSTATE(4);
+	    break;
+
+	case 0x3f:
+	    TSTATE(4);
+	    break;
+
+	case 0x40:
+	    TSTATE(4);
+	    break;
+
+	case 0x41:
+	    TSTATE(4);
+	    break;
+
+	case 0x42:
+	    TSTATE(4);
+	    break;
+
+	case 0x43:
+	    TSTATE(4);
+	    break;
+
+	case 0x44:
+	    TSTATE(4);
+	    break;
+
+	case 0x45:
+	    TSTATE(4);
+	    break;
+
+	case 0x46:
+	    TSTATE(4);
+	    break;
+
+	case 0x47:
+	    TSTATE(4);
+	    break;
+
+	case 0x48:
+	    TSTATE(4);
+	    break;
+
+	case 0x49:
+	    TSTATE(4);
+	    break;
+
+	case 0x4a:
+	    TSTATE(4);
+	    break;
+
+	case 0x4b:
+	    TSTATE(4);
+	    break;
+
+	case 0x4c:
+	    TSTATE(4);
+	    break;
+
+	case 0x4d:
+	    TSTATE(4);
+	    break;
+
+	case 0x4e:
+	    TSTATE(4);
+	    break;
+
+	case 0x4f:
+	    TSTATE(4);
+	    break;
+
+	case 0x50:
+	    TSTATE(4);
+	    break;
+
+	case 0x51:
+	    TSTATE(4);
+	    break;
+
+	case 0x52:
+	    TSTATE(4);
+	    break;
+
+	case 0x53:
+	    TSTATE(4);
+	    break;
+
+	case 0x54:
+	    TSTATE(4);
+	    break;
+
+	case 0x55:
+	    TSTATE(4);
+	    break;
+
+	case 0x56:
+	    TSTATE(4);
+	    break;
+
+	case 0x57:
+	    TSTATE(4);
+	    break;
+
+	case 0x58:
+	    TSTATE(4);
+	    break;
+
+	case 0x59:
+	    TSTATE(4);
+	    break;
+
+	case 0x5a:
+	    TSTATE(4);
+	    break;
+
+	case 0x5b:
+	    TSTATE(4);
+	    break;
+
+	case 0x5c:
+	    TSTATE(4);
+	    break;
+
+	case 0x5d:
+	    TSTATE(4);
+	    break;
+
+	case 0x5e:
+	    TSTATE(4);
+	    break;
+
+	case 0x5f:
+	    TSTATE(4);
+	    break;
+
+	case 0x60:
+	    TSTATE(4);
+	    break;
+
+	case 0x61:
+	    TSTATE(4);
+	    break;
+
+	case 0x62:
+	    TSTATE(4);
+	    break;
+
+	case 0x63:
+	    TSTATE(4);
+	    break;
+
+	case 0x64:
+	    TSTATE(4);
+	    break;
+
+	case 0x65:
+	    TSTATE(4);
+	    break;
+
+	case 0x66:
+	    TSTATE(4);
+	    break;
+
+	case 0x67:
+	    TSTATE(4);
+	    break;
+
+	case 0x68:
+	    TSTATE(4);
+	    break;
+
+	case 0x69:
+	    TSTATE(4);
+	    break;
+
+	case 0x6a:
+	    TSTATE(4);
+	    break;
+
+	case 0x6b:
+	    TSTATE(4);
+	    break;
+
+	case 0x6c:
+	    TSTATE(4);
+	    break;
+
+	case 0x6d:
+	    TSTATE(4);
+	    break;
+
+	case 0x6e:
+	    TSTATE(4);
+	    break;
+
+	case 0x6f:
+	    TSTATE(4);
+	    break;
+
+	case 0x70:
+	    TSTATE(4);
+	    break;
+
+	case 0x71:
+	    TSTATE(4);
+	    break;
+
+	case 0x72:
+	    TSTATE(4);
+	    break;
+
+	case 0x73:
+	    TSTATE(4);
+	    break;
+
+	case 0x74:
+	    TSTATE(4);
+	    break;
+
+	case 0x75:
+	    TSTATE(4);
+	    break;
+
+	case 0x76:
+	    TSTATE(4);
+	    break;
+
+	case 0x77:
+	    TSTATE(4);
+	    break;
+
+	case 0x78:
+	    TSTATE(4);
+	    break;
+
+	case 0x79:
+	    TSTATE(4);
+	    break;
+
+	case 0x7a:
+	    TSTATE(4);
+	    break;
+
+	case 0x7b:
+	    TSTATE(4);
+	    break;
+
+	case 0x7c:
+	    TSTATE(4);
+	    break;
+
+	case 0x7d:
+	    TSTATE(4);
+	    break;
+
+	case 0x7e:
+	    TSTATE(4);
+	    break;
+
+	case 0x7f:
+	    TSTATE(4);
+	    break;
+
+	case 0x80:
+	    TSTATE(4);
+	    break;
+
+	case 0x81:
+	    TSTATE(4);
+	    break;
+
+	case 0x82:
+	    TSTATE(4);
+	    break;
+
+	case 0x83:
+	    TSTATE(4);
+	    break;
+
+	case 0x84:
+	    TSTATE(4);
+	    break;
+
+	case 0x85:
+	    TSTATE(4);
+	    break;
+
+	case 0x86:
+	    TSTATE(4);
+	    break;
+
+	case 0x87:
+	    TSTATE(4);
+	    break;
+
+	case 0x88:
+	    TSTATE(4);
+	    break;
+
+	case 0x89:
+	    TSTATE(4);
+	    break;
+
+	case 0x8a:
+	    TSTATE(4);
+	    break;
+
+	case 0x8b:
+	    TSTATE(4);
+	    break;
+
+	case 0x8c:
+	    TSTATE(4);
+	    break;
+
+	case 0x8d:
+	    TSTATE(4);
+	    break;
+
+	case 0x8e:
+	    TSTATE(4);
+	    break;
+
+	case 0x8f:
+	    TSTATE(4);
+	    break;
+
+	case 0x90:
+	    TSTATE(4);
+	    break;
+
+	case 0x91:
+	    TSTATE(4);
+	    break;
+
+	case 0x92:
+	    TSTATE(4);
+	    break;
+
+	case 0x93:
+	    TSTATE(4);
+	    break;
+
+	case 0x94:
+	    TSTATE(4);
+	    break;
+
+	case 0x95:
+	    TSTATE(4);
+	    break;
+
+	case 0x96:
+	    TSTATE(4);
+	    break;
+
+	case 0x97:
+	    TSTATE(4);
+	    break;
+
+	case 0x98:
+	    TSTATE(4);
+	    break;
+
+	case 0x99:
+	    TSTATE(4);
+	    break;
+
+	case 0x9a:
+	    TSTATE(4);
+	    break;
+
+	case 0x9b:
+	    TSTATE(4);
+	    break;
+
+	case 0x9c:
+	    TSTATE(4);
+	    break;
+
+	case 0x9d:
+	    TSTATE(4);
+	    break;
+
+	case 0x9e:
+	    TSTATE(4);
+	    break;
+
+	case 0x9f:
+	    TSTATE(4);
+	    break;
+
+	case 0xa0:
+	    TSTATE(4);
+	    break;
+
+	case 0xa1:
+	    TSTATE(4);
+	    break;
+
+	case 0xa2:
+	    TSTATE(4);
+	    break;
+
+	case 0xa3:
+	    TSTATE(4);
+	    break;
+
+	case 0xa4:
+	    TSTATE(4);
+	    break;
+
+	case 0xa5:
+	    TSTATE(4);
+	    break;
+
+	case 0xa6:
+	    TSTATE(4);
+	    break;
+
+	case 0xa7:
+	    TSTATE(4);
+	    break;
+
+	case 0xa8:
+	    TSTATE(4);
+	    break;
+
+	case 0xa9:
+	    TSTATE(4);
+	    break;
+
+	case 0xaa:
+	    TSTATE(4);
+	    break;
+
+	case 0xab:
+	    TSTATE(4);
+	    break;
+
+	case 0xac:
+	    TSTATE(4);
+	    break;
+
+	case 0xad:
+	    TSTATE(4);
+	    break;
+
+	case 0xae:
+	    TSTATE(4);
+	    break;
+
+	case 0xaf:
+	    TSTATE(4);
+	    break;
+
+	case 0xb0:
+	    TSTATE(4);
+	    break;
+
+	case 0xb1:
+	    TSTATE(4);
+	    break;
+
+	case 0xb2:
+	    TSTATE(4);
+	    break;
+
+	case 0xb3:
+	    TSTATE(4);
+	    break;
+
+	case 0xb4:
+	    TSTATE(4);
+	    break;
+
+	case 0xb5:
+	    TSTATE(4);
+	    break;
+
+	case 0xb6:
+	    TSTATE(4);
+	    break;
+
+	case 0xb7:
+	    TSTATE(4);
+	    break;
+
+	case 0xb8:
+	    TSTATE(4);
+	    break;
+
+	case 0xb9:
+	    TSTATE(4);
+	    break;
+
+	case 0xba:
+	    TSTATE(4);
+	    break;
+
+	case 0xbb:
+	    TSTATE(4);
+	    break;
+
+	case 0xbc:
+	    TSTATE(4);
+	    break;
+
+	case 0xbd:
+	    TSTATE(4);
+	    break;
+
+	case 0xbe:
+	    TSTATE(4);
+	    break;
+
+	case 0xbf:
+	    TSTATE(4);
+	    break;
+
+	case 0xc0:
+	    TSTATE(4);
+	    break;
+
+	case 0xc1:
+	    TSTATE(4);
+	    break;
+
+	case 0xc2:
+	    TSTATE(4);
+	    break;
+
+	case 0xc3:
+	    TSTATE(4);
+	    break;
+
+	case 0xc4:
+	    TSTATE(4);
+	    break;
+
+	case 0xc5:
+	    TSTATE(4);
+	    break;
+
+	case 0xc6:
+	    TSTATE(4);
+	    break;
+
+	case 0xc7:
+	    TSTATE(4);
+	    break;
+
+	case 0xc8:
+	    TSTATE(4);
+	    break;
+
+	case 0xc9:
+	    TSTATE(4);
+	    break;
+
+	case 0xca:
+	    TSTATE(4);
+	    break;
+
+	case 0xcb:
+	    TSTATE(4);
+	    break;
+
+	case 0xcc:
+	    TSTATE(4);
+	    break;
+
+	case 0xcd:
+	    TSTATE(4);
+	    break;
+
+	case 0xce:
+	    TSTATE(4);
+	    break;
+
+	case 0xcf:
+	    TSTATE(4);
+	    break;
+
+	case 0xd0:
+	    TSTATE(4);
+	    break;
+
+	case 0xd1:
+	    TSTATE(4);
+	    break;
+
+	case 0xd2:
+	    TSTATE(4);
+	    break;
+
+	case 0xd3:
+	    TSTATE(4);
+	    break;
+
+	case 0xd4:
+	    TSTATE(4);
+	    break;
+
+	case 0xd5:
+	    TSTATE(4);
+	    break;
+
+	case 0xd6:
+	    TSTATE(4);
+	    break;
+
+	case 0xd7:
+	    TSTATE(4);
+	    break;
+
+	case 0xd8:
+	    TSTATE(4);
+	    break;
+
+	case 0xd9:
+	    TSTATE(4);
+	    break;
+
+	case 0xda:
+	    TSTATE(4);
+	    break;
+
+	case 0xdb:
+	    TSTATE(4);
+	    break;
+
+	case 0xdc:
+	    TSTATE(4);
+	    break;
+
+	case 0xdd:
+	    TSTATE(4);
+	    break;
+
+	case 0xde:
+	    TSTATE(4);
+	    break;
+
+	case 0xdf:
+	    TSTATE(4);
+	    break;
+
+	case 0xe0:
+	    TSTATE(4);
+	    break;
+
+	case 0xe1:
+	    TSTATE(4);
+	    break;
+
+	case 0xe2:
+	    TSTATE(4);
+	    break;
+
+	case 0xe3:
+	    TSTATE(4);
+	    break;
+
+	case 0xe4:
+	    TSTATE(4);
+	    break;
+
+	case 0xe5:
+	    TSTATE(4);
+	    break;
+
+	case 0xe6:
+	    TSTATE(4);
+	    break;
+
+	case 0xe7:
+	    TSTATE(4);
+	    break;
+
+	case 0xe8:
+	    TSTATE(4);
+	    break;
+
+	case 0xe9:
+	    TSTATE(4);
+	    break;
+
+	case 0xea:
+	    TSTATE(4);
+	    break;
+
+	case 0xeb:
+	    TSTATE(4);
+	    break;
+
+	case 0xec:
+	    TSTATE(4);
+	    break;
+
+	case 0xed:
+	    TSTATE(4);
+	    break;
+
+	case 0xee:
+	    TSTATE(4);
+	    break;
+
+	case 0xef:
+	    TSTATE(4);
+	    break;
+
+	case 0xf0:
+	    TSTATE(4);
+	    break;
+
+	case 0xf1:
+	    TSTATE(4);
+	    break;
+
+	case 0xf2:
+	    TSTATE(4);
+	    break;
+
+	case 0xf3:
+	    TSTATE(4);
+	    break;
+
+	case 0xf4:
+	    TSTATE(4);
+	    break;
+
+	case 0xf5:
+	    TSTATE(4);
+	    break;
+
+	case 0xf6:
+	    TSTATE(4);
+	    break;
+
+	case 0xf7:
+	    TSTATE(4);
+	    break;
+
+	case 0xf8:
+	    TSTATE(4);
+	    break;
+
+	case 0xf9:
+	    TSTATE(4);
+	    break;
+
+	case 0xfa:
+	    TSTATE(4);
+	    break;
+
+	case 0xfb:
+	    TSTATE(4);
+	    break;
+
+	case 0xfc:
+	    TSTATE(4);
+	    break;
+
+	case 0xfd:
+	    TSTATE(4);
+	    break;
+
+	case 0xfe:
+	    TSTATE(4);
+	    break;
+
+	case 0xff:
+	    TSTATE(4);
+	    break;
+
+    }
+}
+
+
+/* END OF FILE */